FPGA Implementation of Integer Loop Delay Estimation with Low Complexity in Undersampling Digital Predistortion System

Abstract In a digital predistortion (DPD) system, accurate loop delay estimation is one of the prerequisites for precise calculation DPD coefficient. Multiplications plural numbers are needed in most conventional algorithms. Based on Euclidean (ELDE) method, this paper proposes simplified (SELDE) method that can avoid operation multiplication numbers. The ELDE and SELDE implemented actual undersampling systems, separately. results experiments prove feasibility effectiveness methods. Compared with hardware resource consumption decreased, mainly reflected reduction registers look-up tables by 41.26% 42.84%, respectively.